The invention relates to processing memory requests that target memory banks.
Many current computer system memory architectures use synchronous random access memories (synchronous RAMs) such as synchronous dynamic random access memories (SDRAMs), SyncLink dynamic random access memories (SLDRAMs), Rambus dynamic random access memories (RDRAMs) and double data rate (DDR) SDRAM memories. The SyncLink standard has been assigned the tentative designation of IEEE-1596.7 by the Microprocessor & Microcomputer Standards Committee (MMSC) of the Institute of Electrical and Electronics Engineers (IEEE). The Rambus.RTM. standard is published by Rambus, Incorporated of Mountain View, Calif.
In addition to providing inherently faster operation than previous types of memories, synchronous RAM may generally be organized into memory banks 12, as depicted in FIG. 1. Banks represent a physical compartmentalization of memory space, where each bank may correspond to a unit or array of physical memory. A bank may be further divided into pages, where a page is typically defined in terms of a row address. All those memory locations in a bank having a common row address are said to be on the same page of memory.
One feature of banked memory systems is that consecutive memory access operations to a common page may be performed faster than consecutive memory access operations directed to different pages within the same bank. For example, referring to FIGS. 1, 2, 3 and 4, to write data to a memory location of an idle bank 12a, a memory interface 10 (of a bridge, for example) may drive lines of a memory bus 11 at time T.sub.0 with signals that indicate a command to activate a page (of the memory bank 12a) that contains the memory location. Afterwards, the page is deemed "open." Next, the memory interface 10 may furnish signals (at time T.sub.3) that indicate a write command and the column address of the memory location. Subsequently, the memory interface 10 may furnish signals that indicate the data to be written to the memory location.
If additional data is to be written to another memory location in the open page, then the memory interface 10 furnishes signals that indicate another write command, the address and the data, as described below. However, for purposes of writing data into another page of the bank 12a, the memory interface 10 must first close the bank 12a via a precharge operation and then activate the bank 12a (via an activate command) to open the other page before proceeding as described above.
The memory interface 10 typically determines whether the next command to be issued to a particular memory bank conflicts with a current state of the bank. For example, the memory interface 10 may receive a memory write request. However, before the memory interface 10 communicates a write command to the memory store data in the targeted bank, the memory interface 10 determines if a bank conflict exists so that the memory interface 10 may take the appropriate action before performing the request. As an example, the targeted memory bank may be precharging and thus, cannot perform the write request. Unfortunately, the bank conflict checks may consume a significant amount of time and generally limit the speed in which a sequence of memory access operations may be performed.